How to Reduce PCB Manufacturing Cost

A lower quote on a weaker specification is not a saving until the product can accept that specification. Every figure below is hypothetical teaching maths. None of it is a fabricator tariff or a BrahmWorks price.

Ask what the quote includes: material, stack, finish, test, impedance, delivery of an array or of singles, and the one-time charges. Two numbers that differ because one omits electrical test are not two prices for the same board. Put the omitted line back before you rank suppliers. Rank them on a specification you are willing to sign.

Then sort changes by whether they touch the schematic. A tighter outline, a standard finish, or a panel that wastes less border can leave the circuit alone. Dropping a layer, removing impedance control, or changing via construction can force a new layout and a new risk. Do the no-schematic changes first, with the fabricator confirming that their process actually prefers them. A rule of thumb from another factory is how boards grow a feature nobody prices and nobody needs.

The hardware product development process is the place to decide which prototype freedoms are temporary. A cost-down that freezes those freedoms into the production note has not reduced cost. It has renamed a prototype.

Four layers are justified by a dense escape, a continuous reference for a fast pair, or a split of power and ground you can defend. They are not justified by "that is how the last board was". Two layers are justified when the routing, the return paths and the noise you can tolerate all survive the attempt. If you have not tried, you have not earned the layer saving. Blind or buried vias, and via-in-pad that needs filling, are paid for in process steps. Use them when the fan-out or the density has no through-hole escape. Using them because the autorouter turned them on is an accident, not a requirement.

Impedance control is a cost when it forces a stack, a coupon and a tolerance you must meet. Specify it on the nets that need it, with a target. Waiving it on nets that need it to make a quote smaller shifts the cost into debug, where it is no longer called PCB cost and is still yours. The same pattern applies to finish. A levelled finish can be enough for the pitch you place. A flat finish can be required for the pitch you place. Pick from the parts, then accept the price. Do not pick from the cheapest line and then change the parts in silence.

Fabricators price a panel more than they price your outline. Your cost per board falls when more good boards fit in the usable area, after borders, fiducials, coupons and the gaps the process needs. A few millimetres added for a logo, a date code in the wrong place, or a connector that sticks out on one side, can drop a whole row. That is often a larger saving than a resistor value, and it is invisible if you only stare at the schematic.

Ask the fabricator for the usable area and the minimum gaps before you freeze the outline. Designing a pretty rectangle and discovering the step-and-repeat afterwards is how the logo becomes the most expensive ink on the product. Rails for assembly are part of this arithmetic. A board that is cheap as a single and expensive once it has the rails the assembler requires was not cheap.

Test access is in the same family. Probe pads that enlarge the board cost money. Removing them can cost more when faults escape or when programming moves from a fixture to a slower station. Treat that as a trade with two prices, not as a purity rule about unused copper.

Invented product: a sensor hub, rectangular, no flex, no gold fingers. The electrical design is assumed, for the exercise, to be routable on two layers. Nobody has routed it yet. The outline is set by a mechanical sketch: 48 mm by 70 mm, plus a small protrusion the industrial designer added for a logo tab.

Teaching panel, invented: usable area 220 mm by 280 mm. Gap and border are modelled as a step of 4 mm beyond each outline dimension. These are not a shop's design rules. They are numbers so the arithmetic can be checked.

Without the logo tab the outline is 48 mm by 70 mm. Step: 52 mm by 74 mm.

Along 220 mm: 220 / 52 = 4.23, so 4 boards. Along 280 mm: 280 / 74 = 3.78, so 3 boards. Count: 4 × 3 = 12 boards on a panel.

With the tab the outline becomes 56 mm by 70 mm. Step: 60 mm by 74 mm.

Along 220 mm: 220 / 60 = 3.67, so 3 boards. Along 280 mm: still 3. Count: 3 × 3 = 9 boards.

Teaching panel price, same specification either way: INR 6,000. Unit if 12 fit: 6,000 / 12 = INR 500. Unit if 9 fit: 6,000 / 9 = INR 667. The tab costs 667 − 500 = INR 167 per board. At a teaching quantity of 1,000 boards that is 167 × 1,000 = INR 1,67,000, for a mark the user may never read. Move the logo into the existing rectangle and the 12-up panel returns, if the fabricator agrees the gaps. Until they agree, the 12 is a sketch.

Layers, still invented: call a four-layer version of the same panel 1.8 times the two-layer panel, so 6,000 × 1.8 = INR 10,800. On the 12-up outline the four-layer unit is 10,800 / 12 = INR 900, against INR 500 on two layers. The difference is INR 400 per board, and 400 × 1,000 = INR 4,00,000 at the teaching quantity. That saving is unearned until the two-layer layout exists and the returns and the noise are accepted. A respin that puts the layers back, even at a teaching INR 80,000 of layout and boards, does not wipe INR 4,00,000, but it does wipe the idea that the saving was already in hand. Do not book INR 400 a unit in a forecast against a layout nobody has finished.

Finish and test are smaller in this particular invention and still easy to confuse with the above. Leave them as separate lines when you ask for quotes. A supplier who is INR 200 cheaper because test is excluded has not beaten the INR 500 unit. They have sold a different board.

• Quotes are normalised: same stack, finish, test, array and one-time charges.
• Changes that do not touch the schematic are listed first.
• The fabricator has confirmed usable panel area and gaps.
• Outline extras, logo tabs and early connectors are checked against boards per panel.
• Assembly rails are included before the unit price is called low.
• Layer count is justified by a layout that exists, or the saving is marked unearned.
• Special vias are required by fan-out, not by an autorouter default.
• Impedance control is specified where needed and waived in writing elsewhere.
• Finish follows the pitch, not the cheapest line.
• Deleted test pads have a priced alternative for programming and fault finding.
• No forecast books a saving the layout has not earned.

Not unless the specification matches. Add back every omitted test, finish, array rail and one-time charge, then compare. A cheap bare board that your assembler rejects, or that you cannot probe, moves the cost into a different invoice. It does not remove it.

When two layers force a larger outline, a failed impedance, or a respin that costs more than the layer difference at the quantity you will actually build. "Always start with two" and "always use four" are both slogans. The panel arithmetic above is the comparison to run, with your own quotes in place of the teaching prices.

Only when the area you free changes the boards per panel or a real process limit, and when programming and diagnosis have another priced method. Removing pads that were not pushing the outline saves no fabrication cost and weakens the test. Shrinking a board that still yields the same count on the panel is the same mistake.

You buy the panel. The unit is the panel cost divided by good boards that fit, after gaps, coupons and rails. A small growth in outline that drops a row raises the unit even when the square millimetres look trivial. Confirm the fit with the fabricator before you defend the outline in a design review.

Bring the normalised quotes, the panel sketch, and a list of savings you have not yet earned with a layout. A review can remove the logo tab from the cost, or it can stop a layer change that the circuit still needs.

Review the next stage with BrahmWorks